Field
Various features relate to a crack stopping configuration for integrated circuits, and, more specifically to a crack stopping structure in wafer level packaging (WLP).
Background
Wafer-level packaging (WLP) is a technology directed to packaging an integrated circuit while still part of the wafer, in contrast to the more conventional method of slicing the wafer into individual circuits (dice) and then packaging them. WLP may be considered a true chip-scale package (CSP) technology, since the resulting package may be practically of the same size as the die. Wafer-level packaging allows integration of wafer fab, packaging, test, and burn-in at wafer level in order to streamline the manufacturing process undergone by a device from silicon start to customer shipment.
A typical die is manufactured by depositing several metal layers and several dielectric layers on top of a substrate. The die is manufactured by using a WLP process. The substrate, metal layers and dielectric layers are what form the circuit elements of the die. Multiple dies are usually manufactured on a wafer. FIG. 1 illustrates a plan view of a wafer 100 that includes several uncut dies 102. Each uncut die includes a substrate, metal layers and dielectric layers. The wafer 100 is then cut into individual/single dies. FIG. 1 also illustrates vertical and horizontal scribe lines 104-106. Scribe lines are portions of the wafer 100 that are cut in order to manufacture the individual dies (e.g., die 102).
FIG. 2 illustrates a side view of a wafer. Specifically. FIG. 2 illustrates a side view of a portion of a wafer 200. The wafer 200 may include several metal and dielectric layers 202, a pad 204, a passivation layer 206, a first insulation layer 208, a first metal layer 210, a second insulation layer 212, and an under bump metallization (UBM) layer 214. FIG. 2 also illustrates a solder ball 216 on the wafer 200. Specifically, the solder ball 216 is coupled to the UBM layer 214. The pad 204, the first metal layer 210 and the UBM layer 214 are a conductive material (e.g., copper). The first insulation layer 208 and the second insulation layer 212 are polyimide layers (PI), polybenzoxazole (PBO) or other polymer layers used for repassivation. FIG. 2 also illustrates a region of the wafer 200 that will be cut to create individual dies. This region of the wafer 200 is illustrated by the scribe line 218, which may correspond to either of the scribe lines 104-106 of FIG. 1.
During a WLP manufacturing process, dies may be separated either by a scribe-and-break method, mechanical sawing, laser dicing, or a combination of these techniques. During laser grooving and/or mechanical sawing, heat affect zones (HAZ) and/or micro cracks may appear, often resulting in device failure. This becomes more severe in extreme low-k (ELK) devices (e.g., configurations of 28 nm and above). In addition, passivation layer delamination after reliability may occur, resulting in device failure.
Accordingly, there is a need for techniques and technologies for preventing or reducing the propagation of cracking and/or chipping of a die.